SPI connection
Connecting to the Blecon Modem over SPI
The Blecon modem can be controlled using a Serial Peripheral Interface transport.
The maximum bitrate supported is 8Mbps, and SPI used in Mode 0 (clock polarity 0 - leading edge rising, clock phase 0 - data sampled on leading edge).
Each transaction uses three phases: a request phase, a processing phase and a response phase. The Chip Select line must remain asserted during the request and response phases, and must be de-asserted in-between during the processing phase.
Once a request has been processed by the modem (processing phase), the module's IRQ line is asserted. The host MCU can then initiate the response phase. During the response phase, the IRQ line is de-asserted by the module.
Data is sent as little endian.
When the modem needs to request communication from the host MCU (when a response or event frame is ready), it asserts its DRDY (Data Ready) line (active high). The DRDY line is cleared immediately when the Chip Select line goes low.
As soon as the Chip Select line goes low, the SRDY (SPI Ready) line is cleared. It is asserted again (active high) once the modem is ready to process another SPI frame. If the host MCU attempts to communicate with the modem when it's not ready, it will receive an empty frame (see below).
The structure of a request frame is:
Text | 1 byte | 2 bytes | n bytes |
|---|---|---|---|
PICO | 0x01 | Request size | Request |
POCI | 0x00 | Ignore | Ignore |
The structure of a response frame is:
Text | 1 byte | 2 bytes | n bytes |
|---|---|---|---|
PICO | 0x00 | Ignored | Ignored |
POCI | 0x01 | Response size | Response |
The structure of an event frame is:
Text | 1 byte |
|---|---|
PICO | 0x00 |
POCI | 0x02 |
The structure of an empty frame is:
Text | n bytes |
|---|---|
PICO | Ignored |
POCI | 0xFF, 0xFF, 0xFF... |
Last modified 1yr ago